Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Clock period constrained minimal buffer insertion in clock trees
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An efficient zero-skew routing algorithm
DAC '94 Proceedings of the 31st annual Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A low-power design method using multiple supply voltages
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Low-swing interconnect interface circuits
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Buffer insertion for clock delay and skew minimization
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Vlsi clock net routing
Clock skew verification in the presence of IR-drop in the power distribution network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnected rings and oscillators as gigahertz clock distribution nets
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A methodology for low power scheduling with resources operating at multiple voltages
Integration, the VLSI Journal
Analysis and verification of interconnected rings as clock distribution networks
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A low-power reduced swing global clocking methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing peak current via opposite-phase clock tree
Proceedings of the 42nd annual Design Automation Conference
Legitimate Skew Clock Routing with Buffer Insertion
Journal of VLSI Signal Processing Systems
Impact of Thermal Gradients on Clock Skew and Testing
IEEE Design & Test
A timing dependent power estimation framework considering coupling
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design of rotary clock based circuits
Proceedings of the 44th annual Design Automation Conference
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Opposite-Phase Clock Tree for Peak Current Reduction
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Low Power Gated Clock Tree Driven Placement
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Low-power rotary clock array design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The implementation and evaluation of a low-power clock distribution network based on EPIC
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock skew optimization considering complicated power modes
Proceedings of the Conference on Design, Automation and Test in Europe
Pulsed-latch-based clock tree migration for dynamic power reduction
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Skew-bounded low swing clock tree optimization
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Low-swing differential conditional capturing flip-flop for LC resonant clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low-power clock tree by distributing the clock signal at a lower voltage and translating it to a higher voltage at the utilization points. Two low-power schemes are used: reduced swing and multiple-supply voltages. We analyze the issue of tree construction and present conclusions relevant to various technology generations according to the NTRS. Our experimental results show that power savings of an average of 45% are possible for a 0.25 µm technology using multiple supply voltages, and about 32% using a single external supply voltage.