Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock Skew Optimization for Peak Current Reduction
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Useful-Skew Clock Routing with Gate Sizing for Low Power Design
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Minimizing peak current via opposite-phase clock tree
Proceedings of the 42nd annual Design Automation Conference
Fast multi-domain clock skew scheduling for peak current reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Power minimization by clock root gating
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Low-power buffered clock tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Although much research effort has been devoted to the minimization of total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by it. In this paper, we propose an opposite-phase clock scheme to reduce the peak current incurred by the clock tree. Our basic idea is to balance the charging and discharging activities. According to the output operation, the clock buffers that transit simultaneously are divided into two groups: half of the clock buffers transit at the same phase of the clock source, while the other half transit at the opposite phase of the clock source. As a consequence, the opposite-phase clock scheme significantly reduces the peak current caused by the clock tree. Experimental data show that our approach can be applied at different design stages in the existing design flow.