IEEE Transactions on Computers
Analysis and design of latch-controlled synchronous digital circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Plasma: an FPGA for million gate systems
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Proceedings of the 39th annual Design Automation Conference
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
UST/DME: a clock tree router for general skew constraints
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Ground bounce in digital VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing peak current via opposite-phase clock tree
Proceedings of the 42nd annual Design Automation Conference
Fast multi-domain clock skew scheduling for peak current reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Minimizing peak power in synchronous logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Clock buffer polarity assignment for power noise reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Power gating scheduling for power/ground noise reduction
Proceedings of the 45th annual Design Automation Conference
Opposite-phase register switching for peak current minimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Opposite-Phase Clock Tree for Peak Current Reduction
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization
Proceedings of the 46th Annual Design Automation Conference
A fast heuristic algorithm for multidomain clock skew scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock buffer polarity assignment for power noise reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal multi-domain clock skew scheduling
Proceedings of the 48th Design Automation Conference
A reconfigurable clock polarity assignment flow for clock gated designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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High speed synchronous digital systems require large switching currents to facilitate rapid signal transitions. These large currents create voltage drops on the power distribution network and necessitate expensive chip packaging with a large number of supply pins. In this paper we propose a novel technique to reduce the dynamic transient current drawn from the supply pins. Our approach is based on sub-dividing the synchronous clocking into multiple sub-clocks with relative skew. This spreads the computation across the entire clock cycle instead of largely occurring at the beginning. Timing constraints must also be obeyed, so that no races or timing errors are introduced. We propose an exact algorithm based on integer linear programming to solve this problem. We have used our method in the design of a 5GHz ECL encoder chip to achieve a factor of two reduction in ground bounce, as shown by HSPICE simulations. We also obtained order-of-magnitude improvements in ground bounce on benchmarks laid out in sub-micron CMOS technology. The approach potentially leads to significant reductions in packaging costs.