IEEE Transactions on Computers
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A parallel algorithm for zero skew clock tree routing
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
Proceedings of the 2003 international symposium on Physical design
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Clock skew bounds estimation under power supply and process variations
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fast multi-domain clock skew scheduling for peak current reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A practical method for multi-domain clock skew optimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Optimal multi-domain clock skew scheduling
Proceedings of the 48th Design Automation Conference
SmipRef: An efficient method for multi-domain clock skew scheduling
Integration, the VLSI Journal
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In the most general form, clock skew scheduling (CSS) generates a dedicated clock delay for each individual sequential component in the clock distribution network in order to minimize the clock period. Multidomain CSS (MDCSS) relieves this requirement. Instead, sequential components are grouped into several clusters (called clock domains), each of which has a uniform clock delay for all registers within that domain. The skew values of clock domains are provided by a set of deskew buffers with electrically programmable phase shifts and injected after the chip is manufactured. This technique is attractive since, due to process variations, it is becoming overwhelmingly difficult to create precise clock network delays for all sequential elements in a design globally. In this paper, we present a fast algorithm for determining the minimum number of clock domains to be used by MDCSS. The exact solution to this problem cannot be found within a reasonable time if the number of clock domains increases beyond three domains. We show that, even with a small-size circuit, in order to obtain the minimum clock period, more than three clock domains may be required. Therefore, a fast heuristic algorithm is needed to identify these domains. To the best of our knowledge, we present the first efficient heuristic algorithm for this problem. For large benchmark circuits, we solve the problem within 14.7 min on average (as high as 31.7 min for the worst case), while a commercial mixed-integer linear program solver cannot finish in over 5 h. Furthermore, our results show that, for 19 out of 21 small- and medium-size benchmarks, our algorithm yields the optimal solution.