IEEE Transactions on Computers
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock Skew Optimization for Peak Current Reduction
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Opposite-phase register switching for peak current minimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Opposite-Phase Clock Tree for Peak Current Reduction
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization
Proceedings of the 46th Annual Design Automation Conference
Analysis of deskew signaling via adaptive timing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast heuristic algorithm for multidomain clock skew scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal multi-domain clock skew scheduling
Proceedings of the 48th Design Automation Conference
A reconfigurable clock polarity assignment flow for clock gated designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SmipRef: An efficient method for multi-domain clock skew scheduling
Integration, the VLSI Journal
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Given several specific clocking domains, the peak current minimization problem can be formulated as a 0-1 integer linear program. However, if the number of binary variables is large, the run time is unacceptable. In this paper, we study the reduction of this high computational expense. Our approach includes the following two aspects. First, we derive the ASAP schedule and the ALAP schedule to prune the redundancies without sacrificing the exactness (optimality) of the solution. Second, we propose a zone-based scheduling algorithm to solve a large circuit heuristically.