Clock Skew Optimization for Peak Current Reduction

Authors:
L. Benini;P. Vuillod;A. Bogliolo;G. De Micheli
Affiliations:
Computer Systems Laboratory, Stanford University, Stanford, CA 94305-9030;Computer Systems Laboratory, Stanford University, Stanford, CA 94305-9030;Computer Systems Laboratory, Stanford University, Stanford, CA 94305-9030;Computer Systems Laboratory, Stanford University, Stanford, CA 94305-9030
Venue:
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Year:
1997

Citing 16
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Abstract

The presence of large current peaks on the power and ground lines isa serious concern for designers of synchronous digitalcircuits. Current peaks are caused by the simultaneous switching ofhighly loaded clock lines and by the signal propagation through thesequential logic elements. In this work we propose a methodology forreducing the amplitude of the current peaks. This result is obtainedby clock skew optimization. We propose an algorithm that, for a givenclock cycle time, determines the clock arrival time at each flip-flopin order to minimize the current peaks while respecting timingconstraint. Our results on benchmark circuits show that currentpeaks can be reduced without penalty on cycle time and average powerdissipation. Our methodology is therefore well-suited for low-powersystems with reduced supply voltage, where low noise margins are aprimary concern.