Timing optimization by gate resizing and critical path identification
DAC '93 Proceedings of the 30th international Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power estimation of cell-based CMOS circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Multi-level logic optimization for low power using local logic transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock Skew Optimization for Peak Current Reduction
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Power reduction and power-delay trade-offs using logic transformations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A predictive system shutdown method for energy saving of event-driven computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power optimization and management in embedded systems
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Transient power management through high level synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimizing Power in ASIC Behavioral Synthesis
IEEE Design & Test
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Adaptive least mean square behavioral power modeling
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Incremental exploration of the combined physical and behavioral design space
Proceedings of the 42nd annual Design Automation Conference
Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages
The Journal of Supercomputing
Scheduling and optimal voltage selection with multiple supply voltages under resource constraints
Integration, the VLSI Journal
Multiple voltage synthesis scheme for low power design under timing and resource constraints
Integrated Computer-Aided Engineering
Register-Transfer Level Transformations for Low-Power Data-Paths
Integrated Computer-Aided Engineering
Regression Models for Behavioral Power Estimation
Integrated Computer-Aided Engineering
Power optimization for simultaneous scheduling and partitioning with multiple voltages
MMACTE'05 Proceedings of the 7th WSEAS International Conference on Mathematical Methods and Computational Techniques In Electrical Engineering
Energy-aware performance optimization for next-generation green network equipment
Proceedings of the 2nd ACM SIGCOMM workshop on Programmable routers for extensible services of tomorrow
Pipelining-based tradeoffs for hardware/software codesign of multimedia systems
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
Green Networking With Packet Processing Engines: Modeling and Optimization
IEEE/ACM Transactions on Networking (TON)
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