On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing optimization for multi-level combinational networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Dynamical identification of critical paths for iterative gate sizing
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Transistor reordering for power minimization under delay constraint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Circuit optimization for minimisation of power consumption under delay constraint
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Hi-index | 0.00 |