Fundamentals of MOS digital integrated circuits
Fundamentals of MOS digital integrated circuits
A unified design representation can work
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Performance-oriented technology mapping
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
LATTIS: an iterative speedup heuristic for mapped logic
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
Timing optimization by gate resizing and critical path identification
DAC '93 Proceedings of the 30th international Design Automation Conference
Performance enhancement of CMOS VLSI circuits by transistor reordering
DAC '93 Proceedings of the 30th international Design Automation Conference
McPOWER: a Monte Carlo approach to power estimation
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Code Generation for Expressions with Common Subexpressions
Journal of the ACM (JACM)
Synthesis of CMOS domino circuits for charge sharing alleviation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Lowering power consumption in concurrent checkers via input ordering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
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In this article we address the problem of optimization of VLSI circuits to minimize power consumption while meeting performance goals. We present a method of estimating power consumption of a basic or complex CMOS gate which takes the internal capacitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. The method is very efficient when used by library-based design styles. We describe a multipass algorithm that makes use of transistor reordering to optimize performance and power consumption of circuits, has a linear time complexity per pass, and converges to a solution in a small number of passes. Transformations in addition to transistor reordering can be used by the algorithm. The algorithm has been benchmarked on several large examples and the results are presented.