Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
LATTIS: an iterative speedup heuristic for mapped logic
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Timing optimization by gate resizing and critical path identification
DAC '93 Proceedings of the 30th international Design Automation Conference
Performance enhancement of CMOS VLSI circuits by transistor reordering
DAC '93 Proceedings of the 30th international Design Automation Conference
Gate oxide leakage and delay tradeoffs for dual-toxcircuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We address the problem of optimization of VLSI circuits to minimize power consumption while meeting performance goals. We present a method of estimating power consumption of a basic or complex CMOS gate which takes the internal capacitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. We describe a multipass algorithm which makes use of transistor reordering to optimize performance and power consumption of circuits and which has a linear time complexity per pass. The algorithm has been benchmarked on several large examples and the results are presented.