Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level network optimization for low power
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Guarded evaluation: pushing power management to logic synthesis/design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Boolean techniques for low power driven re-synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Two-level logic minimization for low power
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Reducing power dissipation after technology mapping by structural transformations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Re-mapping for low power under tight timing constraints
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
An investigation of power delay trade-offs on PowerPC circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Logic transformation for low power synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Data driven power optimization of sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Design rewiring based on diagnosis techniques
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Logic transformation for low-power synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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In this paper we present an efficient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations consist of adding redundant connections or gates so as to reduce the switching activity. Simple and efficient procedures, based on logic implication, for identifying the sources and targets of the redundant connections are presented. Additionally, procedures that permit the designer to tradeoff power and delay after the transformations are described. Results of experiments on the MCNC benchmark circuits are given. The results indicate that significant reduction of the switching activities of a CMOS combinational circuit can be achieved with a very low area overhead and low computational cost.