HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multi-level logic optimization for low power using local logic transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Synthesis of low-power asynchronous circuits in a specified environment
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Trace driven logic synthesis—application to power minimization
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Two-level logic minimization for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power reduction and power-delay trade-offs using logic transformations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-efficient ASIC synthesis of cryptographic sboxes
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
| Hi-index | 0.00 |
Abstract: We study the problem of two-level logic minimization for low power in static CMOS circuits. We start by defining Power Prime Implicants (PPIs) which identify the set of all implicants that are sufficient and necessary for obtaining a minimum power solution. We then provide an efficient algorithm for generating the set of all PPIs of a function. The set of all PPIs is then used in a minimum covering problem to find the best power solution. The feasibility of generating the set of all PPIs and the increased complexity of solving the minimum covering problem are analyzed by deriving an upper bound on the expected number of PPIs which shows it to be linearly proportional to the number of prime implicants of the function. The results of our experiments are then used to draw conclusions on the effectiveness of low power two-level logic minimization.