Algorithms for multilevel logic optimization
Algorithms for multilevel logic optimization
Re-encoding sequential circuits to reduce power dissipation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Exact and approximate methods for calculating signal and transition probabilities in FSMs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic extraction and factorization for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Feedback, correlation, and delay concerns in the power estimation of VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient power estimation for highly correlated input streams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Two-level logic minimization for low power
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Improving the efficiency of power simulators by input vector compaction
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Integrated resynthesis for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Decomposition of logic functions for minimum transition activity
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Logic synthesis for vlsi design
Logic synthesis for vlsi design
| Hi-index | 0.00 |
A trace driven methodology for logic synthesis and optimization is proposed. Given a logic description of a digital circuit C and an expected trace of input vectors T an implementation of C that optimizes a cost function under application of T is derived. This approach is effective in capturing and utilizing the correlations that exist between input signals on an application specific design. The idea is novel since it propose synthesis and optimization at the logic level where the goal is to optimize the average case rather than the worst case for a chosen cost metric. This paper focuses on the development of algorithms for trace driven optimization to minimize the switching power in multi-level networks. The average net power reduction (internal plus I/O power) obtained on a set of benchmark FSMs is 14%, while the average reduction in internal power is 25%. We also demonstrate that the I/O transition activity provides an upper bound on the power reduction that can be achieved by combinational logic synthesis.