McPOWER: a Monte Carlo approach to power estimation
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Low power multiplexer decomposition
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
An exact gate decomposition algorithm for low-power technology mapping
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Trace driven logic synthesis—application to power minimization
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
G-vector: A New Model for Glitch Analysis in Logic Circuits
Journal of VLSI Signal Processing Systems
ON-LINE TESTABLE LOGIC DESIGN FOR FPGA IMPLEMENTATION
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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In this age of portable electronic systems, the problem of logic synthesis for low power has acquired great importance. The most popular approach has been to target the widely-accepted two-phase paradigm of technology-independent optimization and technology mapping for power minimization. Before mapping, each function of a multi-level network is decomposed into two-input gates. How this decomposition is done can have a significant impact on the power dissipation of the final implementation. The problem of decomposition for low power was recently addressed by Pedram et al. (1993). However, they ignore the power consumption due to glitches, which can be a sizeable fraction of the total power. In this paper, we show how to obtain a transition-optimum binary tree decomposition (i.e., the one which has minimum number of transitions in the worst case, including those due to glitches) for some specific functions (AND, OR, and EX-OR) for zero gate delay model. For a non-zero gate delay model, we present conditions under which our algorithm yields an optimum solution for such functions. We propose a straightforward extension of this algorithm for arbitrary functions and Boolean networks. Experimental results on a set of standard combinational benchmarks indicate that on average, our algorithm generates networks (using two-input gates) that have 16% fewer transitions in the worst case than the networks generated by a simple-minded two-input technology-decomposition algorithm implemented in sis, a widely used logic synthesis system.