Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Decomposition of logic functions for minimum transition activity
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Fast factorization method for implicit cube set representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In recent years, a number of logic designtechniques for look-up table (LUT) based FPGAs havebeen proposed. However, none of these address issuessuch as fault detection or testability. This paperpresents an algorithm which maps optimized Booleanexpressions into look-up table based FPGAs. Thismapping automatically incorporates testability featuresinto designs, allowing on-line detection of faults withina FPGA. This is accomplished by utilizing a unique setof cells to implement a design. These cells operate onthe premise of a two-rail checker, thus producing boththe normal and complemented output when a cell isoperating correctly, and two outputs of the same valuein the presence of a fault. Faults generated in anintermediate cell is propagated to the final outputs, thusallowing on-line testability of a FPGA-based logicsystem.