Generation of BDDs from hardware algorithm descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Finding all simple disjunctive decompositions using irredundant sum-of-products forms
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
BDS: a BDD-based logic optimization system
Proceedings of the 37th Annual Design Automation Conference
Solving Graph Optimization Problems with ZBDDs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
ON-LINE TESTABLE LOGIC DESIGN FOR FPGA IMPLEMENTATION
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Journal of Electronic Testing: Theory and Applications
VSOP (valued-sum-of-products) calculator for knowledge processing based on zero-suppressed BDDs
Proceedings of the 2005 international conference on Federation over the Web
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This paper presents a fast weak-division method for implicit cube set representation using Zero-Suppressed Binary Decision Diagrams, which are a new type of Binary Decision Diagram adapted for representing sets of combinations. Our new weak-division algorithm can be executed in a time almost proportional to the size of the graph, regardless of the number of cubes and literals. Based on this technique, we implemented a simple program for optimizing multilevel logic circuits. Experimental results indicate that we can quickly flatten and factorize multilevel logics even for parity functions and full adders, which have never been flattened in other methods. Our method greatly accelerates multilevel logic synthesis systems and enlarges the scale of applicable circuits