Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Xmap: A technology mapper for table-lookup field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A heuristic method for FPGA technology mapping based on the edge visibility
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
BDD based decomposition of logic functions with application to FPGA synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Optimum functional decomposition using encoding
DAC '94 Proceedings of the 31st annual Design Automation Conference
Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Technology mapping for a two-output RAM-based field programmable gate array
EURO-DAC '91 Proceedings of the conference on European design automation
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Partially-dependent functional decomposition with applications in FPGA synthesis and mapping
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Compatible class encoding in hyper-function decomposition for FPGA synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Finding an optimal functional decomposition for LUT-based FPGA synthesis
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Optimum Functional Decomposition for LUT-Based FPGA Synthesis
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
An Implicit Algorithm for Support Minimization during Functional Decomposition
EDTC '96 Proceedings of the 1996 European conference on Design and Test
ON-LINE TESTABLE LOGIC DESIGN FOR FPGA IMPLEMENTATION
ITC '97 Proceedings of the 1997 IEEE International Test Conference
An efficient algorithm for finding the minimal-area FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computing support-minimal subfunctions during functional decomposition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Roth-Karp decomposition is one of the most popular techniques for LUT-based FPGA technology mapping because it can decompose a node into nodes with fewer numbers of fanins. In this paper, we show how to formulate the compatible class encoding problem in Roth-Karp decomposition as a symbolic-output encoding problem in order to exploit the feature of the two-output LUT architecture. Based on this formulation, we also develop an encoding algorithm to minimize the number of LUT's required to implement the logic circuit. Experimental results show that our encoding algorithm can produce promising results in the logic synthesis environment for the two-output LUT architecture.