Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
IEEE Design & Test
A heuristic method for FPGA technology mapping based on the edge visibility
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Area and delay mapping for table-look-up based field programmable gate arrays
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Maximal reduction of lookup-table based FPGAs
EURO-DAC '92 Proceedings of the conference on European design automation
EURO-DAC '92 Proceedings of the conference on European design automation
Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cube-packing and two-level minimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A tutorial on logic synthesis for lookup-table based FPGAs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Rectification method for lookup-table type FPGA's
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BDD-based logic synthesis for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Fast Partitioning Method for PLA-Based FPGAs
IEEE Design & Test
Area and Timing Estimation for Lookup Table Based FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
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We present a new approach for performing technology mapping onto Field Programmable Gate Arrays (FPGAs). We consider one class of FPGAs, based on two-output five-input RAM-based cells, that are used to implement combinational logic functions. We describe a heuristic algorithm for technology mapping that performs a decomposition of the circuit in the FPGA primitives, driven by the information on logic functional sharing. We have implemented the algorithm in the program Hydra. Experimental results shows an average of 20 % to 25 % improvement over other existing programs in mapping area and 67-fold speedup in computing time.