Xmap: A technology mapper for table-lookup field-programmable gate arrays

Amap: A technology mapper for selector-based field-programmable gate arrays

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference

Area and delay mapping for table-look-up based field programmable gate arrays

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Maximal reduction of lookup-table based FPGAs

EURO-DAC '92 Proceedings of the conference on European design automation

A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping

EURO-DAC '92 Proceedings of the conference on European design automation

On area/depth trade-off in LUT-based FPGA technology mapping

DAC '93 Proceedings of the 30th international Design Automation Conference

Sequential synthesis for table look up programmable gate arrays

DAC '93 Proceedings of the 30th international Design Automation Conference

BDD based decomposition of logic functions with application to FPGA synthesis

DAC '93 Proceedings of the 30th international Design Automation Conference

An architecture-independent approach to FPGA routing based on multi-weighted graphs

EURO-DAC '94 Proceedings of the conference on European design automation

Simultaneous depth and area minimization in LUT-based FPGA mapping

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Series-parallel functions and FPGA logic module design

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Technology mapping of sequential circuits for LUT-based FPGAs for performance

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

RASP: a general logic synthesis system for SRAM-based FPGAs

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Optimal clock period FPGA technology mapping for sequential circuits

DAC '96 Proceedings of the 33rd annual Design Automation Conference

A new method to express functional permissibilities for LUT based FPGAs and its applications

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Combining technology mapping and placement for delay-optimization in FPGA designs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

A new retiming-based technology mapping algorithm for LUT-based FPGAs

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

Optimal clock period FPGA technology mapping for sequential circuits

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A tutorial on logic synthesis for lookup-table based FPGAs

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Rectification method for lookup-table type FPGA's

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Power minization in LUT-based FPGA technology mapping

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

BDD-based logic synthesis for LUT-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization

IEEE Design & Test

A Fast Partitioning Method for PLA-Based FPGAs

IEEE Design & Test

Technology Mapping in Circuit Design Aids

IEEE Design & Test

Area and Timing Estimation for Lookup Table Based FPGAs

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Power minimization algorithms for LUT-based FPGA technology mapping

ACM Transactions on Design Automation of Electronic Systems (TODAES)

An efficient algorithm for finding the minimal-area FPGA technology mapping

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Optimality study of logic synthesis for LUT-based FPGAs

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

Efficient LUT-based FPGA technology mapping for power minimization

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

On area/depth trade-off in LUT-based FPGA technology mapping

IEEE Transactions on Very Large Scale Integration (VLSI) Systems