Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
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DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
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FPGA area reduction by multi-output function based sequential resynthesis
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Boolean factoring and decomposition of logic networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Global delay optimization using structural choices
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
KL-cuts: a new approach for logic synthesis targeting multiple output blocks
Proceedings of the Conference on Design, Automation and Test in Europe
TRECO: dynamic technology remapping for timing engineering change orders
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scalable don't-care-based logic optimization and resynthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Delay optimization using SOP balancing
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, w e presen t a new retiming-based technology mapping algorithm for look-up table-based field programmable gate arrays. The algorithm is based on a novel iterative procedure for computing all k-cuts of all nodes in a sequen tialcircuit, in the presence of retiming. The algorithm completely avoids flow computation whic his the bottleneck of previous algorithms. Due to the fact that k is very small in practice, the procedure for computing all k-cuts is v ery fast. Experimental results indicate the overall algorithm is very efficient in practice.