Area and delay mapping for table-look-up based field programmable gate arrays
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Performance-driven simultaneous place and route for row-based FPGAs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multiple FPGA partitioning with performance optimization
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Performance-driven simultaneous place and route for island-style FPGAs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Technology mapping of sequential circuits for LUT-based FPGAs for performance
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Partially-dependent functional decomposition with applications in FPGA synthesis and mapping
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A new retiming-based technology mapping algorithm for LUT-based FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Optimal clock period FPGA technology mapping for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power minimization algorithms for LUT-based FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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