Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs

Simultaneous depth and area minimization in LUT-based FPGA mapping

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

A method for finding good Ashenhurst decompositions and its application to FPGA synthesis

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Technology mapping of sequential circuits for LUT-based FPGAs for performance

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

RASP: a general logic synthesis system for SRAM-based FPGAs

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs

DAC '96 Proceedings of the 33rd annual Design Automation Conference

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Partially-dependent functional decomposition with applications in FPGA synthesis and mapping

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays

FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits

DAC '97 Proceedings of the 34th annual Design Automation Conference

Optimal clock period FPGA technology mapping for sequential circuits

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

BDS: a BDD-based logic optimization system

Proceedings of the 37th Annual Design Automation Conference

BDD-based logic synthesis for LUT-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Incremental physical resynthesis for timing optimization

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

The effect of post-layout pin permutation on timing

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Optimality study of logic synthesis for LUT-based FPGAs

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

FPGA Design Automation: A Survey

Foundations and Trends in Electronic Design Automation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

On K-LUT based FPGA optimum delay and optimal area mapping

MACMESE'08 Proceedings of the 10th WSEAS international conference on Mathematical and computational methods in science and engineering

On area/depth trade-off in LUT-based FPGA technology mapping

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Computing support-minimal subfunctions during functional decomposition

IEEE Transactions on Very Large Scale Integration (VLSI) Systems