Data structures and network algorithms
Data structures and network algorithms
Fibonacci heaps and their uses in improved network optimization algorithms
Journal of the ACM (JACM)
Almost-optimum speed-ups of algorithms for bipartite matching and related problems
STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
Faster scaling algorithms for network problems
SIAM Journal on Computing
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Technology mapping for FPGAs with nonuniform pin delays and fast interconnections
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Placement-driven technology mapping for LUT-based FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
An Implicit Algorithm for Support Minimization during Functional Decomposition
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Incremental physical resynthesis for timing optimization
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-route LUT output polarity selection for timing optimization
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
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In this paper we study the effect of post-layout pin permutation of designs for FPGA devices with non-uniform cell delays. We present a simple, but timing optimal, pin permutation scheme, and report the results of applying the scheme on a set of public logic synthesis benchmark designs that were synthesized and placed by state-of-the-art commercial FPGA design tools configured to maximum optimization level. Despite the preceding optimizations, we still observed an average timing improvement of 3.7%. This demonstrates the importance of fully utilizing non-uniform cell delays during design optimizations for modern FPGA devices and the still presenting potential of improvement.