A synthesis oriented omniscient manual editor
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Incremental physical resynthesis for timing optimization
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
The effect of post-layout pin permutation on timing
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Efficient SAT-based Boolean matching for FPGA technology mapping
Proceedings of the 43rd annual Design Automation Conference
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Incremental learning approach and SAT model for Boolean matching with don't cares
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
To SAT or not to SAT: Ashenhurst decomposition in a large scale
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Building a faster boolean matcher using bloom filter
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
BooM: a decision procedure for boolean matching with abstraction and dynamic learning
Proceedings of the 47th Design Automation Conference
Boolean matching of function vectors with strengthened learning
Proceedings of the International Conference on Computer-Aided Design
Engineering a scalable Boolean matching based on EDA SaaS 2.0
Proceedings of the International Conference on Computer-Aided Design
From design to design automation
Proceedings of the 2014 on International symposium on physical design
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In this paper, we present new Boolean matching methods for lookup table (LUT)-based programmable logic blocks (PLBs) and their applications to PLB architecture evaluations and field programmable gate array (FPGA) technology mapping. Our Boolean matching methods, which are based on functional decomposition operations, can characterize functions for complex PLBs consisting of multiple LUTs (possibly of different sizes) such as Xilinx XC4K CLBs. With these techniques, we conducted quantitative evaluation of four PLB architectures on their functional capabilities. Architecture evaluation results show that the XC4K CLB can implement 98% of six-input and 88% of seven-input functions extracted from MCNC benchmarks, while a simplified PLB architecture is more cost effective in terms of function implementation per LUT bit. Finally, we proposed new technology mapping algorithms that integrate Boolean matching and functional decomposition operations for depth minimization. Technology mapping results show that our PLB mapping approach achieves 12% smaller depth or 15% smaller area in XC5200 FPGAs and 18% smaller depth in XC4K FPGAs, compared to conventional LUT mapping approaches