Building a faster boolean matcher using bloom filter

Authors:
Chun Zhang;Yu Hu;Lingli Wang;Lei He;Jiarong Tong
Affiliations:
State Key Lab of ASIC and System, Fudan University, Shanghai, NS, China;Electrical and Computer Engineering Department, University of Alberta, Alberta, Canada;State Key Lab of ASIC and System, Fudan University, Shanghai, China;Electrical Engineering Department, UCLA, USA, Los Angeles, USA;State Key Lab of ASIC and System, Fudan University, Shanghai, China
Venue:
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Year:
2010

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Abstract

Boolean matching is one of the most important fundamental algorithms in FPGA synthesis and architecture evaluations. However, existing Boolean matchers for FPGAs, even with numerous improvements, are still not scalable to complex PLBs and large circuits. This paper aims to improve the efficiency of Boolean matching using lookup tables implemented by Bloom filters, which can store terabyte-lookup tables with a desktop PC. The key improvement is to efficiently prune a large set of non-implementable functions use the Bloom filter. Using the area-oriented re-synthesis as an application, the experiments on a broad selection of benchmark sets show that the re-synthesis with our improved Boolean matcher is 18X faster than the one with an optimized SAT-based Boolean matcher, while preserving the quality of the re-synthesizer.