Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Technology mapping for electrically programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Amap: A technology mapper for selector-based field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Characterization of Boolean functions for rapid matching in FPGA technology mapping
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An improved synthesis algorithm for multiplexor-based PGA's
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Boolean matching in logic synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Permutation and phase independent Boolean comparison
Integration, the VLSI Journal
Boolean matching using generalized Reed-Muller forms
DAC '94 Proceedings of the 31st annual Design Automation Conference
Boolean matching for incompletely specified functions
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hmap: a fast mapper for EPGAs using extended GBDD hash tables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Efficient Boolean function matching
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Spectral Techniques in Digital Logic
Spectral Techniques in Digital Logic
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Spectral Techniques for Technology Mapping
Spectral Techniques for Technology Mapping
Permissible functions for multioutput components in combinational logic optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting communication complexity for Boolean matching
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generalized matching from theory to application
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
M32: a constructive multilevel logic synthesis system
DAC '98 Proceedings of the 35th annual Design Automation Conference
A new structural pattern matching algorithm for technology mapping
Proceedings of the 38th annual Design Automation Conference
Technology mapping algorithms for domino logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient canonical form for boolean matching of complex functions in large libraries
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A recursive paradigm to solve Boolean relations
Proceedings of the 41st annual Design Automation Conference
Efficient computation of canonical form for Boolean matching in large libraries
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A new canonical form for fast boolean matching in logic synthesis and verification
Proceedings of the 42nd annual Design Automation Conference
Fast Boolean Matching with Don't Cares
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Reducing structural bias in technology mapping
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based Boolean matching for FPGA technology mapping
Proceedings of the 43rd annual Design Automation Conference
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
An efficient cost-based canonical form for Boolean matching
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A unified approach to canonical form-based Boolean matching
Proceedings of the 44th annual Design Automation Conference
Incremental learning approach and SAT model for Boolean matching with don't cares
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
The decomposition tree for analyses of boolean functions
Mathematical Structures in Computer Science
FPGA area reduction by multi-output function based sequential resynthesis
Proceedings of the 45th annual Design Automation Conference
Signature based Boolean matching in the presence of don't cares
Proceedings of the 45th annual Design Automation Conference
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Simulation and SAT-based Boolean matching for large Boolean networks
Proceedings of the 46th Annual Design Automation Conference
A transform-parametric approach to Boolean matching
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Building a faster boolean matcher using bloom filter
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Embedded memory binding in FPGAs
Proceedings of the 47th Design Automation Conference
BooM: a decision procedure for boolean matching with abstraction and dynamic learning
Proceedings of the 47th Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
Simultaneous functional and timing ECO
Proceedings of the 48th Design Automation Conference
Boolean matching of function vectors with strengthened learning
Proceedings of the International Conference on Computer-Aided Design
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When binding a logic network to a set of cells, a fundamental problem is recognizing whether a cell can implement a portion of the network. Boolean matching means solving this task using a formalism based on Boolean algebra. In its simplest form, Boolean matching can be posed as a tautology check. We review several approaches to Boolean matching as well as to its generalization to cases involving don't care conditions and its restriction to specific libraries such as those typical of anti-fuse based FPGAs. We then present a general formulation of Boolean matching supporting multiple-output logic cells.