An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

Performance directed technology mapping for look-up table based FPGAs

DAC '93 Proceedings of the 30th international Design Automation Conference

On area/depth trade-off in LUT-based FPGA technology mapping

DAC '93 Proceedings of the 30th international Design Automation Conference

Optimal clustering for delay minimization

DAC '93 Proceedings of the 30th international Design Automation Conference

Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

An empirical model for accurate estimation of routing delay in FPGAs

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Hybrid FPGA architecture

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

RASP: a general logic synthesis system for SRAM-based FPGAs

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Memory-to-memory connection structures in FPGAs with embedded memory arrays

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Combining technology mapping and placement for delay-optimization in FPGA designs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

A survey of Boolean matching techniques for library binding

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Low power FPGA design—a re-engineering approach

DAC '97 Proceedings of the 34th annual Design Automation Conference

Delay-optimal technology mapping by DAG covering

DAC '98 Proceedings of the 35th annual Design Automation Conference

Synthesis for FPGAs with embedded memory blocks

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Placement-driven technology mapping for LUT-based FPGAs

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays

DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization

IEEE Design & Test

Circuit clustering for delay minimization under area and pin constraints

EDTC '95 Proceedings of the 1995 European conference on Design and Test

Multi-Million Gate FPGA Physical Design Challenges

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Efficient LUT-based FPGA technology mapping for power minimization

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

A fast algorithm for finding common multiple-vertex dominators in circuit graphs

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Efficient SAT-based Boolean matching for FPGA technology mapping

Proceedings of the 43rd annual Design Automation Conference

Optimal simultaneous mapping and clustering for FPGA delay optimization

Proceedings of the 43rd annual Design Automation Conference