An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation

BDD based decomposition of logic functions with application to FPGA synthesis

DAC '93 Proceedings of the 30th international Design Automation Conference

Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs

DAC '96 Proceedings of the 33rd annual Design Automation Conference

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

A new method to express functional permissibilities for LUT based FPGAs and its applications

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Restructuring logic representations with easily detectable simple disjunctive decompositions

Proceedings of the conference on Design, automation and test in Europe