Optimal orientations of cells in slicing floorplan designs
Information and Control
An empirical model for accurate estimation of routing delay in FPGAs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Hierarchical timing-driven partitioning and placement for symmetrical FPAGS
Hierarchical timing-driven partitioning and placement for symmetrical FPAGS
Combining technology mapping and placement for delay-optimization in FPGA designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algorithms for large-scale flat placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
On wirelength estimations for row-based placement
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Arbitrary rectilinear block packing based on sequence pair
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A methodology for fast FPGA floorplanning
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Fast evaluation of sequence pair in block placement by longest common subsequence computation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
DAC '82 Proceedings of the 19th Design Automation Conference
Fast Hierarchical Floorplanning with Congestion and Timing Control
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Standard-Cell Placement Tool for Designs with High Row Utilization
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
A Trade-off Oriented Placement Tool
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Innovate or perish: FPGA physical design
Proceedings of the 2004 international symposium on Physical design
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources
Proceedings of the 41st annual Design Automation Conference
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Floorplan design for multi-million gate FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
LFF algorithm for heterogeneous FPGA floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A delay-optimized universal FPGA routing architecture
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
FPGA placement using space-filling curves: Theory meets practice
ACM Transactions on Embedded Computing Systems (TECS)
Fast unified floorplan topology generation and sizing on heterogeneous FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Run-time generation of partial FPGA configurations for subword operations
Microprocessors & Microsystems
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The recent past has seen a tremendous increase in the size ofdesign circuits that can be implemented in a single FPGA. Theselarge design sizes significantly impact cycle time due to designautomation software runtimes and an increased number ofperformance based iterations. New FPGA physical designapproaches need to be utilized to alleviate some of theseproblems. Hierarchical approaches to divide and conquer thedesign, early estimation tools for design exploration, andphysical optimizations are some of the key methodologies thathave to be introduced in the FPGA physical design tools. Thispaper will investigate the loss/benefit in quality of results due tohierarchical approaches and compare and contrast some of thedesign automation problem formulations and solutions neededfor FPGAs versus known standard cell ASIC approaches.