Interconnect prediction for programmable logic devices
Proceedings of the 2001 international workshop on System-level interconnect prediction
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Multi-Million Gate FPGA Physical Design Challenges
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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A universal FPGA routing Architecture is presented, which ensures that every module in the FPGA including CLBs and IOBs have a uniform interconnect architecture, and the load of interconnect lines is equally distributed. So, this architecture is highly repeatable and the signal delay is predictable and regular. Furthermore, the realization of the Programmable Interconnect Point (PIP) and the BUFFER driver is also optimized to benefit the signal delay up to 5%. The test results of the example chip show the reasonableness of these ideas.