Field-programmable gate arrays
Field-programmable gate arrays
On routability prediction for field-programmable gate arrays
DAC '93 Proceedings of the 30th international Design Automation Conference
Architecture issues and solutions for a high-capacity FPGA
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
High-performance carry chains for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A new high density and very low cost reprogrammable FPGA architecture
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Hybrid product term and LUT based architectures using embedded memory blocks
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Timing-driven placement for hierarchical programmable logic devices
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Routing algorithms and architectures for field-programmable gate arrays
Routing algorithms and architectures for field-programmable gate arrays
Effect of the prefabricated routing track distribution on FPGA area-efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On wirelength estimations for row-based placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect enhancements for a high-speed PLD architecture
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Designing efficient input interconnect blocks for LUT clusters using counting and entropy
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
A delay-optimized universal FPGA routing architecture
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Towards scalable FPGA CAD through architecture
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Location, location, location: the role of spatial locality in asymptotic energy minimization
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Classical interconnect prediction would seem to be a perfect fit for the design of programmable logic architectures (PLDs). Yet theoretical models such as those based on Rent's Rule are usually only used for rough estimates in the early stages of an architecture development. In practice, empirical methods (evaluation via many test designs) dominate the evaluation of fitting and performance for PLD architectures.The primary reasons for this gap between theory and practice are that the models are difficult to extend to fixed architectures with hierarchy and heterogeneous resources and that many of the cost metrics are different between gate-arrays and PLDs.In this paper and the accompanying talk I will survey some of the issues with line-count estimation for the design of PLDs. I will point out some of the inherent differences between the way interconnect is used in PLDs and gate arrays which lead to new opportunities in the development of the theory. Some previous results will show how interconnect is typically researched in the PLD community. For an idealized PLD architecture, I will attempt to define a simple line-count estimation model using the classical theory and compare it to results in practice. I will also present some empirical and anecdotal data useful for understanding the issues and pitfalls involved in architecture evaluation.The primary goal of this work is to motivate new directions in the theory of interconnect prediction and interconnect prediction specifically for PLDs.