Pre-layout estimation of individual wire lengths
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Interconnect prediction for programmable logic devices
Proceedings of the 2001 international workshop on System-level interconnect prediction
Overcoming wireload model uncertainty during physical design
Proceedings of the 2001 international symposium on Physical design
Design technology productivity in the DSM era (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Min-max placement for large-scale timing optimization
Proceedings of the 2002 international symposium on Physical design
Effective partition-driven placement with simultaneous level processing and global net views
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Sequential delay budgeting with interconnect prediction
Proceedings of the 2003 international workshop on System-level interconnect prediction
Wire length prediction in constraint driven placement
Proceedings of the 2003 international workshop on System-level interconnect prediction
Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
Wire length prediction based clustering and its application in placement
Proceedings of the 40th annual Design Automation Conference
Individual wire-length prediction with application to timing-driven placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential delay budgeting with interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
A priori prediction of tightly clustered connections based on heuristic classification trees
Proceedings of the 2006 international workshop on System-level interconnect prediction
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A pre-placement net length estimation technique for mixed-size circuits
Proceedings of the 11th international workshop on System level interconnect prediction
A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
A SimPLR method for routability-driven placement
Proceedings of the International Conference on Computer-Aided Design
MAPLE: multilevel adaptive placement for mixed-size designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Hi-index | 0.03 |
Wirelength estimation in very large scale integration layout is fundamental to any predetailed routing estimate of timing or routability. In this paper, we develop efficient wirelength estimation techniques appropriate for wirelength estimation during top-down floorplanning and placement of cell-based designs. Our methods give accurate, linear-time approaches, typically with sublinear time complexity for dynamic updating of estimates (e.g., for annealing placement). Our techniques offer advantages not only for early on-line wirelength estimation during top-down placement, but also for a posteriori estimation of routed wirelength given a final placement. In developing these new estimators, we have made several contributions, including (1) insight into the contrast between region-based and bounding box-based rectilinear Steiner minimal tree (RStMT) estimation techniques; (2) empirical assessment of the correlations between pin placements of a multipin net that is contained in a block; and (3) new wirelength estimates that are functions of a block's complexity (number of cell instances) and aspect ratio