Individual wire-length prediction with application to timing-driven placement

Authors:
Qinghua Liu;Bo Hu;Malgorzata Marek-Sadowska
Affiliations:
Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA;Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA;Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

Citing 22
Cited 1

A wire length estimation technique utilizing neighborhood density equations

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An analytic net weighting approach for performance optimization in circuit placement

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing driven placement using complete path delays

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Prime: a timing-driven placement tool using a piecewise linear resistive network approach

DAC '93 Proceedings of the 30th international Design Automation Conference
Timing driven placement for large standard cell circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timing influenced layout design

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A sensitivity based placer for standard cells

GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Pre-layout estimation of individual wire lengths

SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Can recursive bisection alone produce routable placements?

Proceedings of the 37th Annual Design Automation Conference
The interpretation and application of Rent's rule

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Edge separability based circuit clustering with application to circuit partitioning

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Timing driven placement using physical net constraints

Proceedings of the 38th annual Design Automation Conference
Dragon2000: standard-cell placement tool for large industry circuits

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Wire length prediction in constraint driven placement

Proceedings of the 2003 international workshop on System-level interconnect prediction
Fine granularity clustering for large scale placement problems

Proceedings of the 2003 international symposium on Physical design
Timing-driven placement using design hierarchy guided constraint generation

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Wire length prediction based clustering and its application in placement

Proceedings of the 40th annual Design Automation Conference
Improved a priori terconnect predictions and technology extrapolation in the GTX system

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Chip layout optimization using critical path weighting

DAC '84 Proceedings of the 21st Design Automation Conference
An evaluation of bipartitioning techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A delay budgeting algorithm ensuring maximum flexibility in placement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On wirelength estimations for row-based placement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we address the problem of individual wire-length prediction and demonstrate its usefulness in timing-driven placement. Many researchers have observed that different placement algorithms produce different individual wire lengths. We postulate that to obtain accurate results, individual wire-length prediction should be coupled with the placement flow. We embed the wire-length prediction into the clustering step of our fast placer implementation (FPI) framework [19]. The predicted wire lengths act as constraints for the simulated annealing refinement stage, which guides the placement toward a solution fulfilling them. Experimental results show that our prediction process yields accurate results without loss of quality and incurs only a small cost in placement effort. We successfully apply the wire-length prediction technique to timing-driven placement. Our new slack assignment algorithm with predicted wire lengths (p-SLA) gives on average an 8% improvement in timing performance compared with the conventional modified zero-slack algorithm (m-ZSA).