Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A wire length estimation technique utilizing neighborhood density equations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An analytic net weighting approach for performance optimization in circuit placement
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A sensitivity based placer for standard cells
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Pre-layout estimation of individual wire lengths
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Edge separability based circuit clustering with application to circuit partitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Timing driven placement using physical net constraints
Proceedings of the 38th annual Design Automation Conference
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Fine granularity clustering for large scale placement problems
Proceedings of the 2003 international symposium on Physical design
Timing-driven placement using design hierarchy guided constraint generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
An evaluation of bipartitioning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A delay budgeting algorithm ensuring maximum flexibility in placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On wirelength estimations for row-based placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
Individual wire-length prediction with application to timing-driven placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire length prediction-based technology mapping and fanout optimization
Proceedings of the 2005 international symposium on Physical design
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A pre-placement net length estimation technique for mixed-size circuits
Proceedings of the 11th international workshop on System level interconnect prediction
A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Experiments show that lengths of individual wires are different for different placement algorithms. To achieve accurate wire length prediction, some knowledge of a placer's details is necessary. We postulate that wire length prediction should be coupled with placement flow to obtain accurate results. In this paper, we embed wire length prediction into our constraint-driven placer, developed in Fast Placer Implementation (FPI) framework [15]. We predict individual wire lengths during the clustering step. The predicted wire lengths act as constraints for the simulated annealing refinement stage, which guides the placement towards a solution fulfilling the predictions. Experimental results show that our wire length prediction process yields accurate results without quality loss at a small cost of placement effort. This is the first time that constraints have been used to guide placement and thus increase the accuracy of wire length prediction.