A pre-placement individual net length estimation model and an application for modern circuits

Authors:
A. Farshidi;L. Behjat;L. Rakai;B. Fathi
Affiliations:
Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada;Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada;Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada;Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada
Venue:
Integration, the VLSI Journal
Year:
2011

Citing 28
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Abstract

With the advances in integrated circuit (IC) technology, managing the individual and total interconnect is becoming one of the main challenges facing designers. An individual a-priori length estimation model can be a useful tool in helping designers obtain lower net lengths and congestion of interconnect. In this paper, the main characteristics that need to be considered while designing an individual a-priori length estimation technique for today's integrated circuits are discussed. A model that includes some of the most prevalent characteristics is designed and tested using the most current benchmark circuits released by IBM. In addition, one application of the length estimation is proposed in which a predictor-corrector framework for clustering that can be used to improve the results of placement is implemented. This model shows that the corrector step can improve the final placement results by up to 33% for special cases.