RQL: global placement via relaxed quadratic spreading and linearization
Proceedings of the 44th annual Design Automation Conference
DPlace2.0: a stable and efficient analytical placement based on diffusion
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A pre-placement net length estimation technique for mixed-size circuits
Proceedings of the 11th international workshop on System level interconnect prediction
Handling complexities in modern large-scale mixed-size placement
Proceedings of the 46th Annual Design Automation Conference
RegPlace: a high quality open-source placement framework for structured ASICs
Proceedings of the 46th Annual Design Automation Conference
CROP: fast and effective congestion refinement of placement
Proceedings of the 2009 International Conference on Computer-Aided Design
CRISP: congestion reduction by iterated spreading during placement
Proceedings of the 2009 International Conference on Computer-Aided Design
ITOP: integrating timing optimization within placement
Proceedings of the 19th international symposium on Physical design
SafeChoice: a novel clustering algorithm for wirelength-driven placement
Proceedings of the 19th international symposium on Physical design
History-based VLSI legalization using network flow
Proceedings of the 47th Design Automation Conference
A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
RegularRoute: an efficient detailed router with regular routing patterns
Proceedings of the 2011 international symposium on Physical design
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
The ISPD-2011 routability-driven placement contest and benchmark suite
Proceedings of the 2011 international symposium on Physical design
Quadratic placement with single-iteration linear system solver
Proceedings of the 24th symposium on Integrated circuits and systems design
A SimPLR method for routability-driven placement
Proceedings of the International Conference on Computer-Aided Design
SimPL: an effective placement algorithm
Proceedings of the International Conference on Computer-Aided Design
A fast discrete placement algorithm for FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Keep it straight: teaching placement how to better handle designs with datapaths
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
MAPLE: multilevel adaptive placement for mixed-size designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
A size scaling approach for mixed-size placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Proceedings of the 49th Annual Design Automation Conference
GDRouter: interleaved global routing and detailed routing for ultimate routability
Proceedings of the 49th Annual Design Automation Conference
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
A compiler for scalable placement and routing of brain-like architectures
Proceedings of the 2013 ACM international symposium on International symposium on physical design
SimPL: an algorithm for placing VLSI circuits
Communications of the ACM
Sub-quadratic objectives in quadratic placement
Proceedings of the Conference on Design, Automation and Test in Europe
Cell density-driven detailed placement with displacement constraint
Proceedings of the 2014 on International symposium on physical design
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts
Proceedings of the 2014 on International symposium on physical design
ICCAD-2013 CAD contest in placement finishing and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
POLAR: placement based on novel rough legalization and refinement
Proceedings of the International Conference on Computer-Aided Design
Clock power minimization using structured latch templates and decision tree induction
Proceedings of the International Conference on Computer-Aided Design
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In this paper, we present FastPlace 3.0 - an efficient and scalable multilevel quadratic placement algorithm for large-scale mixed-size designs. The main contributions of our work are: (1) A multilevel global placement framework, by incorporating a two-level clustering scheme within the flat analytical placer FastPlace (Viswanathan and Chu, 2005) and Viswanathan et al., 2006), (2) An efficient and improved iterative local refinement technique that can handle placement blockages and placement congestion constraints. (3) A congestion aware standard-cell legalization technique in the presence of blockages. On the ISPD-2005 placement benchmarks (Nam et al., 2005), our algorithm is 5.12times, 11.52times and 16.92times faster than mPL6, Capo10.2 and APlace2.0 respectively. In terms of wirelength, we are on average, 2% higher as compared to mPL6 and 9% and 3% better as compared to Capo10.2 and APlace2.0 respectively. We also achieve competitive results compared to a number of academic placers on the placement congestion constrained ISPD-2006 placement benchmarks (Nam, 2006).