Advances in linear and integer programming
Advances in linear and integer programming
DAC '98 Proceedings of the 35th annual Design Automation Conference
Regularity driven logic synthesis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The ISPD2005 placement contest and benchmark suite
Proceedings of the 2005 international symposium on Physical design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
Working Set Selection Using Second Order Information for Training Support Vector Machines
The Journal of Machine Learning Research
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Modern Circuit Placement: Best Practices and Results
Modern Circuit Placement: Best Practices and Results
Quantifying academic placer performance on custom designs
Proceedings of the 2011 international symposium on Physical design
Congestion analysis for global routing via integer programming
Proceedings of the International Conference on Computer-Aided Design
SimPL: an effective placement algorithm
Proceedings of the International Conference on Computer-Aided Design
Keep it straight: teaching placement how to better handle designs with datapaths
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Extraction of functional regularity in datapath circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Network flow based datapath bit slicing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs
Proceedings of the International Conference on Computer-Aided Design
Clock power minimization using structured latch templates and decision tree induction
Proceedings of the International Conference on Computer-Aided Design
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This work presents PADE, a new placer with automatic datapath extraction and evaluation. PADE applies novel data learning techniques to train, predict, and evaluate potential datapaths using high-dimensional data such as netlist symmetrical structures, initial placement hints and relative area. Extracted datapaths are mapped to bit-stack structures that are aligned and simultaneously placed with the random logic. Results show at least 7% average total Half-Perimeter Wire Length (HPWL) and 12% Steiner Wire Length (StWL) improvements on industrial hybrid benchmarks and at least 2% average total HPWL and 3% StWL improvements on ISPD 2005 contest benchmarks. To the best of our knowledge, this is the first attempt to link data learning, datapath extraction with evaluation, and placement and has the tremendous potential for pushing placement state-of-the-art for modern circuits which have datapath and random logics.