A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
Decoupling capacitance efficient placement for reducing transient power supply noise
Proceedings of the 2009 International Conference on Computer-Aided Design
Completing high-quality global routes
Proceedings of the 19th international symposium on Physical design
Wirelength-driven force-directed 3D FPGA placement
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
Ripple: an effective routability-driven placer by iterative cell movement
Proceedings of the International Conference on Computer-Aided Design
SimPL: an effective placement algorithm
Proceedings of the International Conference on Computer-Aided Design
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
Proceedings of the International Conference on Computer-Aided Design
A fast discrete placement algorithm for FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Keep it straight: teaching placement how to better handle designs with datapaths
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
MAPLE: multilevel adaptive placement for mixed-size designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
WRIP: logic restructuring techniques for wirelength-driven incremental placement
Proceedings of the great lakes symposium on VLSI
Exploiting die-to-die thermal coupling in 3D IC placement
Proceedings of the 49th Annual Design Automation Conference
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
SimPL: an algorithm for placing VLSI circuits
Communications of the ACM
Sub-quadratic objectives in quadratic placement
Proceedings of the Conference on Design, Automation and Test in Europe
Ripple 2.0: high quality routability-driven placement via global router integration
Proceedings of the 50th Annual Design Automation Conference
Cell density-driven detailed placement with displacement constraint
Proceedings of the 2014 on International symposium on physical design
Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs
Proceedings of the 2014 on International symposium on physical design
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts
Proceedings of the 2014 on International symposium on physical design
POLAR: placement based on novel rough legalization and refinement
Proceedings of the International Conference on Computer-Aided Design
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The force-directed quadratic placer ldquoKraftwerk2,rdquo as described in this paper, is based on two main concepts. First, the force that is necessary to distribute the modules on the chip is separated into the following two components: a hold force and a move force. Both components are implemented in a systematic manner. Consequently, Kraftwerk2 converges such that the module overlap is reduced in each placement iteration. The second concept of Kraftwerk2 is to use the ldquoBound2Boundrdquo net model, which accurately represents the half-perimeter wirelength (HPWL) in the quadratic cost function. Aside from these features, this paper presents additional details about Kraftwerk2. An approach to remove halos (free space) around large modules is described, and a method to control the module density is presented. In order to choose the important tradeoff between runtime and quality, a systematic quality control is shown. Furthermore, plots demonstrating the convergence of Kraftwerk2 are presented. Results using various benchmark suites demonstrate that Kraftwerk2 offers both high quality and excellent computational efficiency.