TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Circuit Optimization by Rewiring
IEEE Transactions on Computers
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Incremental Placement for Timing Optimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Diffusion-based placement migration
Proceedings of the 42nd annual Design Automation Conference
Theory of wire addition and removal in combinational Boolean networks
Microelectronic Engineering
SafeResynth: A new technique for physical synthesis
Integration, the VLSI Journal
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
ECR: a low complexity generalized error cancellation rewiring scheme
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents WRIP - a Wirelength-driven Rewiring-based Incremental Placement which effectively reduces wirelength of the optimized placement of industrial large-scale standard cell designs. WRIP uses a powerful logic synthesis technique called logic rewiring which restructures the local circuits while preserving the logic functionality and reduces the wirelength under an accurate estimation of the half perimeter wirelength (HPWL) metric. We integrated WRIP into an industrial EDA tool and tested it upon several real designs with hundreds of thousands of movable objects. Tested on circuits which has been fully optimized by the state-of-the-art industrial placement tool, our experiments showed that on average WRIP reduces wirelength by 2.25% after placement and 2.45% after global routing in HPWL and Steiner WL model respectively. The runtime of WRIP is only about half an hour for the largest tested ASIC circuit. This is the first attempt to fully integrate powerful logic synthesis into industrial placement tools with real-life effectiveness and efficiency.