A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Layout driven logic synthesis for FPGAs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Circuit partitioning with logic perturbation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementation and use of SPFDs in optimizing Boolean networks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Circuit Optimization by Rewiring
IEEE Transactions on Computers
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Single-pass redundancy addition and removal
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A new enhanced SPFD rewiring algorithm
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Further improve circuit partitioning using GBAW logic perturbation techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
Theory of wire addition and removal in combinational Boolean networks
Microelectronic Engineering
How much can logic perturbation help from netlist to final routing for FPGAs
Proceedings of the 44th annual Design Automation Conference
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast detection of node mergers using logic implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Rewiring using IRredundancy removal and addition
Proceedings of the Conference on Design, Automation and Test in Europe
Perturb and simplify: multilevel Boolean network optimizer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On applying erroneous clock gating conditions to further cut down power
Proceedings of the 16th Asia and South Pacific Design Automation Conference
WRIP: logic restructuring techniques for wirelength-driven incremental placement
Proceedings of the great lakes symposium on VLSI
Almost every wire is removable: a modeling and solution for removing any circuit wire
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Rewiring is known to be a new class of logic restructuring technique at least equally powerful in flexibility compared to other logic transformation techniques while being wiring-sensitive, a property particularly useful for interconnect based circuit synthesis processes. One of the most mature rewiring techniques is the ATPG-based Redundancy Addition and Removal (RAR) technique which adds a redundant alternative wire to make an originally irredundant target wire become redundant and thus removable. In this paper, we propose a new Error Cancellation based Rewiring scheme (ECR) which can also do non-RAR based rewiring operations with high efficiency. Based on the notion of error cancellation, we analyze and reformulate the rewiring problem and develop a generalized rewiring scheme being able to detect more rewiring cases which are not obtainable by existing schemes while still maintains low runtime complexity. Comparing with the most recent non-RAR rewiring tool IRRA, the total number of alternative wires found by our approach is about twice while CPU time is just slightly more (26%) upon benchmarks pre-optimized by rewriting of ABC.