Layout driven logic synthesis for FPGAs

Perturb and simplify: multi-level boolean network optimizer

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Logic clause analysis for delay optimization

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Re-engineering of timing constrained placements for regular architectures

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Circuit partitioning with logic perturbation

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Reducing power dissipation after technology mapping by structural transformations

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Fast Boolean optimization by rewiring

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Timing optimization by an improved redundancy addition and removal technique

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Integrating symbolic techniques in ATPG-based sequential logic optimization

DATE '99 Proceedings of the conference on Design, automation and test in Europe

An integrated algorithm for combined placement and libraryless technology mapping

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Synthesis for multiple input wires replacement of a gate for wiring consideration

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Power and delay reduction via simultaneous logic and placement optimization in FPGAs

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Circuit partitioning with coupled logic restructuring techniques

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Improved alternative wiring scheme applying dominator relationship

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Further improve circuit partitioning using GBAW logic perturbation techniques

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)

An Improved Approach for AlternativeWires Identi.cation

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

SAT-controlled redundancy addition and removal: a novel circuit restructuring technique

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

ECR: a low complexity generalized error cancellation rewiring scheme

Proceedings of the 47th Design Automation Conference

ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme

ACM Transactions on Design Automation of Electronic Systems (TODAES)