A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Layout driven logic synthesis for FPGAs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Timing optimization by an improved redundancy addition and removal technique
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Sequential Logic Synthesis
Redundancy Identification and Removal Based on Implicit State Enumeration
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the optimization power of redundancy addition and removal techniques for sequential circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Combining retiming and sequential redundancy addition and removal for sequential logic optimization
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
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