Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On the optimization power of retiming and resynthesis transformations
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Integrating symbolic techniques in ATPG-based sequential logic optimization
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Generalized reasoning scheme for redundancy addition and removal logic optimization
Proceedings of the conference on Design, automation and test in Europe
Design and implementation verification of finite state systems
Design and implementation verification of finite state systems
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper attempts to determine the capabilities of existing Redundancy Addition and Removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the Retiming and Resynthesis (RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the Sequential Redundancy Addition and Removal over the Retiming and Resynthesis techniques.