Digital logic testing and simulation
Digital logic testing and simulation
The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Redundancies and don't cares in sequential logic synthesis
Journal of Electronic Testing: Theory and Applications
Unified Methods for VLSI Simulation and Test Generation
Unified Methods for VLSI Simulation and Test Generation
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
On the over-specification problem in sequential ATPG algorithms
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Multi-level logic optimization of FSM networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences
IEEE Transactions on Computers
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Sequential redundancy identification using recursive learning
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Integrating symbolic techniques in ATPG-based sequential logic optimization
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
IEEE Transactions on Computers
A Hierarchical Test Generation Approach for Large Controllers
IEEE Transactions on Computers
Isomorph-Redundancy in Sequential Circuits
IEEE Transactions on Computers
Logic Synthesis and Verification
Simulation-Based Engineering for Industrial Competitive Advantage
IEEE Design & Test
Testing Core-Based Systems: A Symbolic Methodology
IEEE Design & Test
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
On undetectable faults in partial scan circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Surprises in Sequential Redundancy Identification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
8.3 On Removing Redundant Faults in Synchronous Sequential Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC'94 Proceedings of the 1994 international conference on Test
Is IDDQ yield loss inevitable?
ITC'94 Proceedings of the 1994 international conference on Test
On achieving complete testability of synchronous sequential circuits with synchronizing sequences
ITC'94 Proceedings of the 1994 international conference on Test
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