Statecharts: A visual formalism for complex systems
Science of Computer Programming
A protocol test generation procedure
Computer Networks and ISDN Systems
STATEMATE: A Working Environment for the Development of Complex Reactive Systems
IEEE Transactions on Software Engineering
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Speed up of test generation using high-level primitives
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Hierarchical test generation under intensive global functional constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
FsmTest: functional test generation for sequential circuits
Integration, the VLSI Journal
A complete testing strategy based on interacting and hierarchical FSMs
Integration, the VLSI Journal
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
IEEE Transactions on Computers
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Test generation for multiple state-table faults in finite-state machines
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Synthesis for testability of large complexity controllers
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Protocol Conformance Testing Using Multiple UIO Sequences
Proceedings of the IFIP WG6.1 Ninth International Symposium on Protocol Specification, Testing and Verification IX
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
| Hi-index | 14.98 |
A testing approach targeted at Hardware Description Language (HDL)-based specifications of complex control devices is proposed. For such architectures, gate-level test pattern generators require insertion of scan paths to enable the flat gate-level representations to be efficiently handled. In contrast, we present a testing methodology based on the hierarchical finite state machine model. Our approach allows the generation of compact test sets with very high stuck-at fault coverages, without any design-for-testability logic other than hardware reset. This method can be used any time the functional information is available together with the gate-level structural description. High fault coverages are achieved with smaller test lengths and execution times with respect to state-of-the-art gate-level test pattern generators.