Taking into account asynchronous signals in functional test of complex circuits
DAC '84 Proceedings of the 21st Design Automation Conference
Hierarchical test generation under intensive global functional constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automatic partitioning for deterministic test
EURO-DAC '92 Proceedings of the conference on European design automation
Efficient orthonormality testing for synthesis with pass-transistor selectors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient use of large don't cares in high-level and logic synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A Hierarchical Test Generation Approach for Large Controllers
IEEE Transactions on Computers
Logic Synthesis and Verification
New Techniques for Deterministic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
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We propose a general methodology to speed up the test generation process for circuits with high-level primitives. Our search procedure is a variation of depth first search that tries to fully exploit the capabilities of a computer to execute complex arithmetic and logical operations. We present techniques for signal value justification, and fault propagation, which are used by our algorithm. We have implemented a dependency-directed backtracking method to speed up our algorithm. This methodology has been applied to six circuits and the results are found to be very encouraging.