Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On redundancy and untestability in sequential circuits
On redundancy and untestability in sequential circuits
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
One-Pass Redundancy Identification and Removal
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Identifying sequentially untestable faults using illegal states
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
IEEE Transactions on Computers
8.3 On Removing Redundant Faults in Synchronous Sequential Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Untestable fault identification through enhanced necessary value assignments
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
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A sequential redundancy identification procedure is presented. Based on uncontrollability analysis and recursive learning techniques, this procedure identifies c-cycle redundancies in large circuits, without simplifying assumptions or state transition information. The proposed procedure can identify redundant faults which require conflicting assignments on multiple lines. In this sense, it is a generalization of FIRES, a state-of-the-art redundancy identification algorithm. A modification of the proposed procedure is also presented for identifying untestable faults. Experimental results on ISCAS benchmarks demonstrate that these two procedures can efficiently identify a large portion of c-cycle redundant and untestable faults.