On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
IDDQ testing as a component of a test suite: the need for several fault coverage metrics
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
IDDQ testing in CMOS digital ASICs
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
QUIETEST: a methodology for selecting IDDQ test vectors
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Warning: 100% Fault Coverage May Be Misleading!!
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Detection of "Undetectable" Faults Using IDDQ Testing
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
The Economics of Guardband Placement
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
CMOS IC reliability indicators and burn-in economics
ITC '98 Proceedings of the 1998 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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IDDQ testing is a powerful way to improve the quality of low fault coverage tests, and to detect defects that are hard or impossible to detect using traditional voltage testing methods. However, it appears that there is some yield loss associated with IDDQ testing, where yield loss means that devices passing burn-in and system tests fail IDDQ test. This paper gives reasons why such yield loss is inevitable, and must be considered when making a decision whether or not to use IDDQ testing. We also present some evidence backing up this speculation, and a brief economic model to help in making IDDQ testing decisions.