Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
Redundancies and don't cares in sequential logic synthesis
Journal of Electronic Testing: Theory and Applications
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Compact test generation for bridging faults under I/sub DDQ/ testing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A bridging fault model where undetectable faults imply logic redundancy
Proceedings of the conference on Design, automation and test in Europe
Journal of Electronic Testing: Theory and Applications
Robust fault models where undetectable faults imply logic redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Given a combinational logic circuit, we find a subset of lines R that has the following property. Every line g in the circuit has a representative line r in R such that g and r carry identical values for any input combination of the circuit. This problem has applications in logic optimization as well as in testing. We define the problem, discuss its applications, describe a solution based on structural analysis and on functional analysis that uses logic simulation, and present experimental results. Considering logic optimization, every line g in the circuit can be replaced by a fanout branch of its representative r, and the logic driving g can be removed. Circuit size is thus reduced. We demonstrate that circuit reduction based on the set R can be used as a preprocessing step to reduce the run time of logic optimization procedures, without compromising solution quality. We also consider pairs of lines that always carry opposite values and show how they can be used to further reduce circuit size.