On adaptive diagnostic test generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits
IEEE Transactions on Computers
Compaction of IDDQ Test Sequence Using Reassignment Method
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Fault models and test generation for IDDQ testing: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
IDDQ Test and Diagnosis of CMOS Circuits
IEEE Design & Test
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Fast Algorithms for Computer IDDQ Tests for Combination Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
6.2 A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Dynamic Test Compaction for Bridging Faults
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
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Abstract: We propose a procedure to generate compact test sets for bridging faults under I/sub DDQ/ testing. Several techniques are employed to achieve compact test sets. Heuristics developed for stuck-at faults are shown to be effective in this context. The techniques especially designed for bridging faults are based on the observation that the yet-undetected faults can be represented using sets of lines and that a minimum test set size is obtained if the line sets representing yet-undetected faults are halved with every additional test vector. Logic blocks called bit-adders allow the partitioning of the line sets using a test generator for stuck-at faults, without having to determine in advance how the lines in a given set will be divided. Thus partitioning can be performed in a cost effective way for any line set size. Experimental results show that the test sets generated by the proposed procedure are smaller than those obtained by previously proposed procedures.